module sig_gate_gen #(
    parameter integer NCNTS = 10
) (
    input  sys_clk,
    input  rst_n,
    input  start_i,
    output sig_gate_o
);

  localparam Width = $clog2(NCNTS);

  localparam reg [1:0] S_IDLE = 2'b00;
  localparam reg [1:0] S_CNT = 2'b01;
  localparam reg [1:0] S_END = 2'b10;

  reg [Width-1:0] cnt_reg;

  reg [1:0] r_state;
  reg [1:0] state_next;

  reg r_gate;

  always @(*) begin
    state_next = r_state;
    case (r_state)
      S_IDLE: begin
        if (start_i) begin
          state_next = S_CNT;
        end
      end
      S_CNT: begin
        if (cnt_reg == NCNTS - 1) begin
          state_next = S_END;
        end
      end
      S_END: begin
        if (~start_i) begin
          state_next = S_IDLE;
        end else begin
          state_next = S_CNT;
        end
      end
      default: begin
        state_next = S_IDLE;
      end
    endcase
  end

  always @(posedge sys_clk or negedge rst_n) begin
    if (~rst_n) begin
      r_state <= S_IDLE;
    end else begin
      r_state <= state_next;
    end
  end

  always @(posedge sys_clk or negedge rst_n) begin
    if (~rst_n) begin
      cnt_reg <= 0;
    end else begin
      if (r_state == S_CNT) begin
        if (cnt_reg == NCNTS - 1) begin
          cnt_reg <= 0;
        end else begin
          cnt_reg <= cnt_reg + 1'b1;
        end
      end else begin
        cnt_reg <= 0;
      end
    end
  end

  always @(posedge sys_clk or negedge rst_n) begin
    if (~rst_n) begin
      r_gate <= 0;
    end else if (r_state == S_CNT) begin
      r_gate <= 1;
    end else begin
      r_gate <= 0;
    end
  end

  assign sig_gate_o = r_gate;

endmodule
